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<title>veriT | Formal Methods Tools</title>
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<h1><a href="/">Formal Methods Tools</a></h1>
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<a href="/tools/">Tools</a>
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<a href="/taxonomies/">Data</a>
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<main>
<div id="page-header">
<h1>veriT</h1>
<span class="subtitle">SMT Solver</span>
<div id="link-list">
<ul>
<li><a href="https://www.verit-solver.org/" target="_blank" rel="noopener"><i class="fa-solid fa-home"></i>&nbsp;&nbsp;Homepage</a></li>
<li><a href="https://github.com/SRI-CSL/yices2" target="_blank" rel="noopener"><i class="fa-brands fa-github"></i>&nbsp;&nbsp;Source Code</a></li>
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<h2>At a Glance</h2>
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href="/applications">
Applications
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id="applications_smt-solver"
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SMT Solver
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Developers
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href="/developers/loria">
LORIA
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<a
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id="developers_uliege"
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href="/developers/uliege">
ULiege
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href="/inputs">
Inputs
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<a
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href="/inputs/smtlib2">
SMTLIB2
</a>
<a
class="term-link"
id="inputs_dimacs"
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href="/inputs/dimacs">
DIMACS
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Interfaces
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CLI
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BSD
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Maintenance
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Actively Maintained
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</td>
</tr>
</tbody>
</table>
</section>
<section>
<h2>Description</h2>
<p>veriT is an SMT solver developed by LORIA and ULiege. It supports a wide range of theories and is designed for use in formal verification, automated reasoning, and related research areas. veriT accepts input in SMT-LIB2 and DIMACS formats and provides a command-line interface for ease of integration into verification workflows. The solver is actively maintained and distributed under the BSD license, making it suitable for both academic and industrial applications.</p>
</section>
<section id="publications">
<h2>Publications</h2>
<ul>
<li>
<strong>Reliable Reconstruction of Fine-Grained Proofs in a Proof Assistant</strong>
(2021)
by Schurr, Hans-Jörg et. al.
| Appears in <em>CADE 2021</em>
| Published by Springer
| <a href="https://doi.org/10.1007/978-3-030-79876-5_26" target="_blank" rel="noopener">10.1007/978-3-030-79876-5_26</a>
</li>
</ul>
</section>
<p class="time">Updated <time datetime="2025-06-07T00:00:00&#43;00:00">June 7, 2025</time></p>
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