Formal Methods Tools

At a Glance

Developers SRI International
Domains Software Verification Hardware Verification Embedded Systems
Formalisms first-order logic SMT-LIB quantifier logic bit-vectors arrays uninterpreted functions arithmetic
Interactions CLI C API OCaml API Python Bindings
Languages SMT-LIB Yices language C OCaml Python
Purposes Verification Tools Analysis Tools
Systems Discrete Systems Concurrent Systems
Techniques Theorem Proving SMT Solving Model Checking

Description

Yices is a high-performance SMT solver and theorem prover developed by SRI International. It is widely used for checking the satisfiability of logical formulas over various theories, including arithmetic, bit-vectors, arrays, and uninterpreted functions. Yices supports the SMT-LIB standard and its own input language, and provides APIs for several programming languages, making it suitable for integration into formal verification, program analysis, and constraint solving tools.

Features

Publications