At a Glance
| Applications | SMT Solver |
| Developers | LORIA ULiege |
| Inputs | SMTLIB2 DIMACS |
| Interfaces | CLI |
| Licenses | BSD |
| Maintenance | Actively Maintained |
Description
veriT is an SMT solver developed by LORIA and ULiege. It supports a wide range of theories and is designed for use in formal verification, automated reasoning, and related research areas. veriT accepts input in SMT-LIB2 and DIMACS formats and provides a command-line interface for ease of integration into verification workflows. The solver is actively maintained and distributed under the BSD license, making it suitable for both academic and industrial applications.
Publications
- Reliable Reconstruction of Fine-Grained Proofs in a Proof Assistant (2021) by Schurr, Hans-Jörg et. al. | Appears in CADE 2021 | Published by Springer | 10.1007/978-3-030-79876-5_26
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