90 lines
6.0 KiB
XML
90 lines
6.0 KiB
XML
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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom">
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<channel>
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<title>BSD on Formal Methods Tools</title>
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<link>https://fmtools.fyi/licenses/bsd/</link>
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<description>Recent content in BSD on Formal Methods Tools</description>
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<generator>Hugo</generator>
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<language>en-us</language>
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<lastBuildDate>Sat, 07 Jun 2025 00:00:00 +0000</lastBuildDate>
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<atom:link href="https://fmtools.fyi/licenses/bsd/index.xml" rel="self" type="application/rss+xml" />
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<item>
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<title>Concuerror</title>
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<link>https://fmtools.fyi/tools/mc/concuerror/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mc/concuerror/</guid>
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<description><p>Concuerror is a stateless model checking tool for Erlang programs.</p></description>
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</item>
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<item>
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<title>cvc4</title>
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<link>https://fmtools.fyi/tools/sat-smt/cvc4/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/sat-smt/cvc4/</guid>
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<description><p>

<div style="display: flex; align-items: center; gap: 8px;">
 <span style="display: inline-block; width: 12px; height: 12px; border-radius: 50%; background: rgb(240, 85, 85);"></span>
 <span style="display:none">[</span>
 
 <span style="color: rgb(240, 85, 85); font-size: 1rem;">Not Maintained Since 2021</span>
 
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</div>
cvc4 is an automatic theorem prover for SMT problems. It is succeeded by <a href="../cvc5" >cvc5</a></p></description>
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</item>
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<item>
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<title>cvc5</title>
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<link>https://fmtools.fyi/tools/sat-smt/cvc5/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/sat-smt/cvc5/</guid>
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<description><p>cvc5 is an automatic theorem prover for SMT problems.</p></description>
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</item>
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<item>
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<title>Intrepyd</title>
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<link>https://fmtools.fyi/tools/mc/intrepyd/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mc/intrepyd/</guid>
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<description><p>

<div style="display: flex; align-items: center; gap: 8px;">
 <span style="display: inline-block; width: 12px; height: 12px; border-radius: 50%; background: rgb(240, 85, 85);"></span>
 <span style="display:none">[</span>
 
 <span style="color: rgb(240, 85, 85); font-size: 1rem;">Not Maintained Since 2021</span>
 
 <span style="display:none">]</span>
</div>
Intrepyd is a python module that provides a simulator and a model checker in form of a rich API, to allow the rapid prototyping of formal methods algorithms for the rigorous analysis of circuits, specifications, models.</p></description>
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</item>
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<item>
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<title>LTSmin</title>
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<link>https://fmtools.fyi/tools/mc/ltsmin/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mc/ltsmin/</guid>
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<description><p>LTSmin started out as a generic toolset for manipulating labelled transition systems. Meanwhile the toolset was extended to a a full (LTL/CTL/μ-calculus) model checker, while maintaining its language-independent characteristics.</p></description>
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</item>
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<item>
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<title>Pnmc</title>
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<link>https://fmtools.fyi/tools/mc/pnmc/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mc/pnmc/</guid>
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<description><p>Pnmc is a symbolic model checker for Petri nets.</p></description>
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</item>
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<item>
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<title>TAPAAL</title>
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<link>https://fmtools.fyi/tools/mc/tapaal/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mc/tapaal/</guid>
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<description><p>TAPAAL is a tool for verification of timed-arc petri nets</p></description>
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</item>
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<item>
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<title>TLA+</title>
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<link>https://fmtools.fyi/tools/mod/tlaplus/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/mod/tlaplus/</guid>
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<description><p>TLA+ is a high-level language for modeling programs and systems&ndash;especially concurrent and distributed ones.</p></description>
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</item>
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<item>
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<title>Vampire</title>
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<link>https://fmtools.fyi/tools/sat-smt/vampire/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/sat-smt/vampire/</guid>
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<description><p>Vampire is a theorem prover.</p></description>
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</item>
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<item>
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<title>veriT</title>
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<link>https://fmtools.fyi/tools/sat-smt/verit/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/sat-smt/verit/</guid>
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<description><p>veriT is an SMT solver developed by LORIA and ULiege. It supports a wide range of theories and is designed for use in formal verification, automated reasoning, and related research areas. veriT accepts input in SMT-LIB2 and DIMACS formats and provides a command-line interface for ease of integration into verification workflows. The solver is actively maintained and distributed under the BSD license, making it suitable for both academic and industrial applications.</p></description>
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</item>
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<item>
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<title>Zipperposition</title>
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<link>https://fmtools.fyi/tools/sat-smt/zipperposition/</link>
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<pubDate>Sat, 07 Jun 2025 00:00:00 +0000</pubDate>
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<guid>https://fmtools.fyi/tools/sat-smt/zipperposition/</guid>
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<description><p>Zipperposition is an automated theorem prover for first-order logic with equality and theories.</p></description>
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</item>
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</rss>
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