Wrap up SAT/SMT

tools/sat-smt/verit.md

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+date = 2025-06-07
+draft = false
+
+title = 'veriT'
+subtitle = 'SMT Solver'
+
+links = [
+    { title = "Homepage", url = "https://www.verit-solver.org/", icon = 'fa-solid fa-home'},
+    # { title = "Source Code", url = "https://github.com/SRI-CSL/yices2", icon = 'fa-brands fa-github' },
+    # { title = "Documentation", url = "https://yices.csl.sri.com/yices2-documentation.html" }
+]
+
+applications = ['SMT Solver']
+developers = ['LORIA', 'ULiege']
+licenses = ['BSD']
+inputs = ['SMTLIB2', 'DIMACS']
+interfaces = ['CLI']
+maintenance = ['Actively Maintained']
+
+publications = ['Schurr2021']
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+
+veriT is an SMT solver developed by LORIA and ULiege. It supports a wide range of theories and is designed for use in formal verification, automated reasoning, and related research areas. veriT accepts input in SMT-LIB2 and DIMACS formats and provides a command-line interface for ease of integration into verification workflows. The solver is actively maintained and distributed under the BSD license, making it suitable for both academic and industrial applications.