24 lines
1.0 KiB
Markdown
24 lines
1.0 KiB
Markdown
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date = 2025-06-07
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draft = false
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title = 'veriT'
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subtitle = 'SMT Solver'
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links = [
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{ title = "Homepage", url = "https://www.verit-solver.org/", icon = 'fa-solid fa-home'},
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{ title = "Source Code", url = "https://github.com/SRI-CSL/yices2", icon = 'fa-brands fa-github' },
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# { title = "Documentation", url = "https://yices.csl.sri.com/yices2-documentation.html" }
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]
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applications = ['SMT Solver']
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developers = ['LORIA', 'ULiege']
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licenses = ['BSD']
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inputs = ['SMTLIB2', 'DIMACS']
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interfaces = ['CLI']
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maintenance = ['Actively Maintained']
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publications = ['Schurr2021']
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veriT is an SMT solver developed by LORIA and ULiege. It supports a wide range of theories and is designed for use in formal verification, automated reasoning, and related research areas. veriT accepts input in SMT-LIB2 and DIMACS formats and provides a command-line interface for ease of integration into verification workflows. The solver is actively maintained and distributed under the BSD license, making it suitable for both academic and industrial applications. |